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HM671400H Series
4,194,304-words x 1-bit High Speed Static Random Access Memory
ADE-203-086G(Z) Rev. 8 Aug. 28, 1996 Features
* * * * * * * 4194304-words x 1 bit organization Directly TTL compatible input and output +5.0 V Single Supply Completely static memory No clock or timing strobe required Super fast access time: 15/20 ns (Max) Revolutional Pin Arrangement
Ordering Information
Type No. HM671400HJP-15 HM671400HJP-20 4M x 1 Organization Access time 15 ns 20 ns Package 400 mil 32 pin Plastic SOJ (CP-32DB)
Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice.
HM671400H Series
Pin Arrangement
A0 A1 A2 A3 A4 A5 CS VCC VSS Din WE A6 A7 A8 A9 A10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A21 A20 A19 A18 A17 A16 OE VSSO VCCO Dont A15 A14 A13 A12 A11 NC
Pin Description
Pin Name A0 to A21 Din Dout WE CS OE VCC VCCO VSSO VSS NC Function Address Input Data Input Data Output Write Enable Chip Select Output Enable +5 V Power Supply Output Buffer Power Supply Output Buffer Ground Ground Not Connect
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HM671400H Series
Block Diagram
A6 A20 A1 A7 A14 A8 A13 A9 A4 A18 Din Input Data Control
V CC V SS Row Decoder Memory Matrix 1024 x 4096 V CCO V SSO Column I/O Column Decoder Dout
A15 A2 A19 A3 A21 A0 A12A10 A11 A5 A16A17
CS WE OE
Function Table
CS H L L L L WE X H H L L OE X H L H L Mode Not Selected Output Disable Read Write Write Output High Z High Z Data Out High Z High Z VCC Current I SB , I SB1 I CC, I CC1 I CC, I CC1 I CC, I CC1 I CC, I CC1
3
HM671400H Series
Absolute Maximum Ratings
Item Supply Voltage *
1 1
Symbol VCC VT PT Topr Tstg (Bias) Tstg
Rating -0.5 to + 7.0 -0.5 to VCC + 0.5 1.0/1.5 * 0 to +70 -10 to + 85 -55 to + 125
2
Unit V V W C C C
Voltage on any pin relative to V SS * Power dissipation Operating Temperature Range
Storage Temperature Range (with bias) Storage Temperature Range
Notes: 1. With respect to V SS = VSSO 2. PT = 1.5 W is guaranteed under the minimum air flow exceeding 500 linear feet per minute.
Under the dc and ac specifications shown in the Tables, this device is tested under the minimum transverse air flow exceeding 500 linear feet per minute.
Recommended DC Operating Conditions (0C Ta 70C)
Item Supply Voltage Symbol VCC, VCCO VSS , VSSO Input High Voltage Input Low Voltage VIH VIL Min 4.5 0.0 2.2 -0.5 Typ 5.0 0.0 -- -- Max 5.5 0.0 VCC + 0.5 0.8 Unit V V V V
4
HM671400H Series
DC and Operating Characteristics (VCC = VCCO = 5.0 V 10%, V SS = VSSO = 0 V, Ta = 0 to +70C)
15 Item Input Leakage Current Output Leakage Current Symbol IILII IILO I Test Conditions VCC = 5.5 V, VIN = 0 V to VCC CS = VIH or OE = VIH, WE = VIL VOUT = 0 V to VCC CS = VIL, IOUT = 0 mA Min. cycle, IOUT = 0 mA CS = VIH Min. cycle CS = VIH All input fixed and V IN = VIH or VIL CS V CC - 0.2 V VIN 0.2 V or VIN V CC - 0.2 V I OL = 8 mA I OH = -4 mA Min -- -- Max 2 10 Min -- -- 20 Max 2 10 Unit A A
Operating Power Supply Current Average Operating Current Standby Power Supply Current
I CC I CC1 I SBAC I SBDC I SB1
-- -- -- -- --
120 170 100 20 10
-- -- -- -- --
120 150 80 20 10
mA mA mA mA mA
Output Low Voltage Output High Voltage
VOL VOH
-- 2.4
0.4 --
-- 2.4
0.4 --
V V
5
HM671400H Series
AC Characteristics (VCC = VCCO = 5.0 V 10%, V SS = VSSO = 0 V, Ta = 0C to 70C, unless otherwise noted.)
Read Cycle
15 Item Read Cycle Time Address Access Time Chip Select Access Time Chip Selection to Output in Low Z Output Enable to Output Valid Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Hold from Address Change Symbol t RC t AA t ACS t LZ * * t OE t OLZ * * t HZ * * t OH
1, 2 1, 2 1, 2
20 Min 20 -- -- 5 -- 2 0 5 Max -- 20 20 -- 10 -- 8 -- Unit ns ns ns ns ns ns ns ns
Min 15 -- -- 5 -- 2 0 5
Max -- 15 15 -- 8 -- 7 --
Notes: 1. This parameter is sampled and not 100% tested. 2. Transition is measured 200 mV from steady state voltage with specified loading in Load(B).
Write Cycle
15 Item Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Disable to Output in High Z Output Active from End of Write Symbol t WC * t CW t AW t AS t WP t WR t DW t DH t WZ * *
2, 2, 2, 3 3 1
20 Min 20 15 15 0 15 3 10 0 0 0 2 Max -- -- -- -- -- -- -- -- 8 8 -- Unit ns ns ns ns ns ns ns ns ns ns ns
Min 15 12 12 0 12 3 8 0 0 0 2
Max -- -- -- -- -- -- -- -- 7 7 --
t OHZ * * t OW * *
3
Notes: 1. All Write Cycle timings are referenced from the last valid address to the first transitioning address. 2. This parameter is sampled and not 100% tested. 3. Transition is measured 200 mV from steady state voltage with specified with loading Load(B).
6
HM671400H Series
Capacitance (Ta = 25C, f = 1 MHz)
Item Input Capacitance Output Capacitance Note: Symbol CIN *
1 1
Max 6 8
Unit pF pF
Test Condition VIN = 0 V VOUT = 0 V
COUT *
1. This parameter is sampled and not 100% tested.
AC Test Conditions * * * * * Input pulse levels: V SS to 3.0 V Input timing reference levels: 1.5 V Output Load: See figure Input rise and fall times: 4 ns Output reference levels: 1.5 V
+5V +5V
Output 255
480 30 pF *
Output 255
480 5 pF *
Output Load A
Output Load B (for tHZ, tLZ, tOHZ, tOLZ, tWZ, & tOW) * including scope and jig capacitance
7
HM671400H Series
Timing Waveforms
Read Cycle-1 *1
t RC Address t AA OE t OE CS t OLZ t OHZ t HZ Data Valid High Impedance Note: 1. WE = VIH t OH
t ACS t LZ Data Out
Read Cycle-2 *1, * 2, * 3
t RC Address t OH Data Out Notes: 1. 2. 3. Previous Date Valid WE = VIH CS = VIL OE = VIL t AA Date Valid t OH
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HM671400H Series
Read Cycle-3 *1, * 2, * 3
t RC
CS t ACS t LZ Data Out High Impedance Notes: 1. 2. 3.
t HZ Date Valid
WE = VIH CS = VIL Address valid prior to or coincident with CS transition low.
Write Cycle-1 *1 (OE = H, WE Controlled)
t WC Address t CW CS t AS WE t AW t WP
*1
t WR
t DW Data In Date Valid
t DH
Data Out Note: 1.
High Impedance A write occurs during the overlap of a low CS and a low WE (tWP).
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HM671400H Series
Write Cycle-2 *1 (OE = H, CS Controlled)
t WC Address t AS CS t AW WE t WP
*1
t CW
t WR
t DW Data In Date Valid
t DH
Data Out Note: 1.
High Impedance A write occurs during the overlap of a low CS and a low WE (tWP).
10
HM671400H Series
Write Cycle-3 *1 (OE = Clocked, WE Controlled)
tWC Address
OE tCW CS tAW tAS WE tOHZ Data Out High Impedance tDW Data In Note: 1. Data Valid A write occurs during the overlap of a low CS and a low WE (tWP). tDH tOLZ tWP *1 tWR
11
HM671400H Series
Write Cycle-4 *1, *2 (OE = Clocked, CS Controlled)
tWC Address
OE tAS CS
*2
tCW
tAW tWP *1 WE tDW Data In Data Valid tDH tWR
Data Out Notes: 1. 2.
High Impedance A write occurs during the overlap of a low CS and a low WE (tWP). If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in a high impedance state.
12
HM671400H Series
Write Cycle-5 *1, * 2, * 3 (OE = L, WE Controlled)
t WC Address t CW CS t AW t AS WE t WZ Data Out
*2
t WP
*1
t WR
t OW High Impedance
t OH
*3
t DW Data In Notes: 1. 2. 3. Data Valid
t DH
A write occurs during the overlap of a low CS and a low WE (tWP). During this period, I/O pins are output state so that the input signals of opposite phase to the outputs must nit be applied. Output data is the same phase of write data of this write cycle.
13
HM671400H Series
Write Cycle-6 *1, * 2 (OE = L, CS Controlled)
t WC Address t AS CS t AW t WP *1 WE t LZ Data Out t WZ
*2
t CW
t WR
High Impedance t DW t DH
Data In Notes: 1. 2.
Data Valid A write occurs during the overlap of a low CS and a low WE (tWP). If the CS low transition occurs after the WE low transition, output remain in a high impedance state.
14
HM671400H Series
Package Dimension
HM761400HJP Series (CP-32DB)
20.71 21.08 Max
Unit : mm
32
17 10.16 0.13 11.18 0.13
1
3.50 0.26
1.265 Max
0.43 0.10
1.27 0.10
0.63 Min
9.40 0.25
2.85 0.12
0.74
16
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HM671400H Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
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